AIデータセンター向けディスアグリゲーテッド・メモリ・アーキテクチャ市場シェア分析、業界動向と統計、成長予測 2026-2031年

AIデータセンター向けディスアグリゲーテッド・メモリ・アーキテクチャ（分離型メモリ・アーキテクチャ）市場の規模は、2025年に8億9,000万米ドル、2026年に12億8,000万米ドルとなり、2026年から2031年にかけて年平均成長率（CAGR）38.27%で拡大し、2031年には64億7,000万米ドルに達するとMordor Intelligenceでは予測しています。

この成長を牽引しているのは、データセンター設計における実質的な転換です。AIワークロードの増大により、従来のサーバー・メモリ構成を拡張するスピードよりも速いペースで、サーバーごとのDRAM容量の限界に達する事態が生じているためです。また、AIデータセンター向けディスアグリゲーテッド・メモリ・アーキテクチャ市場は、単にハードウェアが利用可能かどうかという段階を超えつつあります。現在、購入者はオーケストレーション・ソフトウェア、テレメトリ、メモリ・ティアリング、そして認定（クオリフィケーション）サポートといった要素をより重視するようになっているからです。もう一つの重要な変化として、運用事業者がプール型メモリを単なる大容量化の手段としてではなく、サーバー台数、消費電力、およびリフレッシュ処理に伴う非効率性を削減する手段として捉えるようになっている点が挙げられます。こうした状況は、コントローラー、スイッチ、モジュール、管理ソフトウェアを統合し、安定した本番稼働用スタックを構築できるベンダーにとっての好機となります。さらに、この市場の拡大は、ソブリンAI（国家主導のAI）の構築、地域データセンターの拡張、そして異種混在（ヘテロジニアス）なCXL環境の運用を容易にするソフトウェア主導の制御レイヤーといった分野でも、新たな機会を創出し続けるでしょう。

レポートの主なポイント

• コンポーネント別では、2025年のAIデータセンター向けディスアグリゲーテッド・メモリ・アーキテクチャ市場において、メモリ・モジュールが44.13%のシェアを占めて首位となりました。一方、ソフトウェアおよび管理プラットフォームは、2031年まで年平均成長率（CAGR）39.18%で拡大すると予測されています。
• メモリ技術別では、2025年にDRAMが61.76%のシェアを占めました。一方、階層型メモリ（DRAM + NAND）は、2031年までCAGR 38.97%で成長すると予測されています。
• アーキテクチャ・タイプ別では、2025年の同市場において、ダイレクト・アタッチ・メモリ拡張（Direct Attached Memory Expansion）が51.36%のシェアを占めました。一方、ファブリック・アタッチ・メモリ（Fabric Attached Memory）は、2031年までCAGR 38.91%で拡大すると予測されています。
• 用途別では、2025年の収益においてAI学習（AI Training）が39.94%を占めました。一方、大規模言語モデル（LLM）のサービングは、2031年までCAGR 39.36%で拡大すると予測されています。
• エンドユーザー別では、2025年の同市場においてハイパースケーラーが55.18%のシェアを占めました。一方、クラウド・サービス・プロバイダーは、2031年までCAGR 39.11%で成長すると予測されています。
• 地域別では、2025年に北米が収益シェア46.28%で首位となりました。一方、アジア太平洋地域は、2031年までCAGR 39.09%という最も高い成長率を記録すると予測されています。

アーキテクチャ別：初期は「ダイレクト・アタッチ」が優勢、方向性は「ファブリック・アタッチ」が決定づける

2025年のAIデータセンター市場におけるメモリ分離（ディスアグリゲーテッド・メモリ）アーキテクチャにおいて、「ダイレクト・アタッチ（直接接続）」型のメモリ拡張が51.36%を占めました。これは、保守的な傾向を持つ購入者にとって、最も検証・導入が容易なアーキテクチャであるためです。CXL対応CPUと互換性のある拡張モジュールさえあれば初期導入が可能であり、技術的・組織的な導入障壁を低く抑えられます。そのため、AIデータセンター市場におけるメモリ分離アーキテクチャは、運用事業者が戦略計画の中で「プーリング」や「ファブリック」について頻繁に言及しているにもかかわらず、初期段階では依然としてダイレクト・アタッチ方式が主流となっています。「スイッチド・メモリ・プーリング」や「ラックスケール・メモリ分離」がそれに続きますが、これらはいずれも、より複雑なトポロジ、高度なソフトウェア連携、そしてホストとデバイスにまたがる徹底した検証作業を必要とします。2026年の調査では、有意なプーリングの利点はサーバー64台規模のクラスタで現れ始める一方、低遅延通信の管理はサーバー16台程度の小規模な「アイランド（独立領域）」内であれば容易であることが示されており、この知見がベンダーによるポッド設計のあり方に影響を与えています。

「ファブリック・アタッチ」型メモリは、コンポーザブル（構成変更可能）なAIデータセンターという長期的な設計目標に合致しており、2031年まで年平均成長率（CAGR）38.91%で成長すると予測されています。Marvell社の「Structera 30260」はこの目的のために投入された製品であり、260レーンと4TB/sの総帯域幅を備え、CPU、GPU、XPU間での動的なメモリ割り当てを実現することを目指しています。Panmnesia社も同様の方向性を追求しており、PCIe 6.4およびCXL 3.2対応の「Fusion Switch」を推進しています。同社はこれを、ポートベース・ルーティングによるCXL 3.2を実装した初のシリコン製品であると説明しています[2]。こうしたデバイスの存在感が高まっていることは、AIデータセンター市場におけるメモリ分離アーキテクチャが、単一のホストの境界を超え、より広範なファブリックを介したメモリ・アクセスに必要なハードウェア基盤を構築し始めていることを示しています。とはいえ、移行は緩やかなものにとどまるでしょう。ラック・トポロジを再設計することなく即座にメリットを享受したいと考える多くの購入者にとって、ダイレクト・アタッチ方式での導入が依然として最も現実的な選択肢だからです。したがって、AIデータセンター向けメモリ分離アーキテクチャの業界では、今後数年にわたり複数のアーキテクチャが並行して展開される見通しです。具体的には、ダイレクト・アタッチ・モデルが現在の収益を支える一方で、ファブリック・アタッチ・モデルが将来のロードマップを形作っていくことになるでしょう。

Disaggregated Memory Architecture For AI Data Centers Market Analysis by Mordor Intelligence

The disaggregated memory architecture market size for AI data centers is projected to be USD 0.89 billion in 2025, USD 1.28 billion in 2026, and reach USD 6.47 billion by 2031, growing at a CAGR of 38.27% from 2026 to 2031. Growth is being shaped by a practical shift in data center design, because AI workloads are exhausting per-server DRAM limits faster than operators can scale conventional server memory layouts. The disaggregated memory architecture for the AI data center market is also moving beyond a hardware-availability story, as buyers now place greater weight on orchestration software, telemetry, memory tiering, and qualification support. Another important change is that operators are treating pooled memory as a way to reduce server counts, power use, and refresh inefficiency, rather than solely as a path to higher capacity. This creates room for vendors that can tie together controllers, switches, modules, and management software into a stable production stack. It also means the disaggregated memory architecture for AI data centers market will keep opening opportunities in sovereign AI builds, regional data center expansion, and software-led control layers that make heterogeneous CXL environments easier to run.

Key Report Takeaways

• By component, Memory Modules led with 44.13% of the disaggregated memory architecture for AI data centers market size in 2025, while Software and Management Platforms are projected to expand at a 39.18% CAGR through 2031.
• By memory technology, DRAM held 61.76% share in 2025, while Tiered Memory (DRAM + NAND) is projected to grow at a 38.97% CAGR through 2031.
• By architecture type, Direct Attached Memory Expansion accounted for 51.36% of the disaggregated memory architecture for AI data centers market size in 2025, while Fabric Attached Memory is projected to advance at a 38.91% CAGR through 2031.
• By application, AI Training accounted for 39.94% of revenue in 2025, while Large Language Model Serving is projected to expand at a 39.36% CAGR through 2031.
• By end user, Hyperscalers held 55.18% of the disaggregated memory architecture for AI data centers market share in 2025, while Cloud Service Providers are projected to grow at a 39.11% CAGR through 2031.
• By geography, North America led with 46.28% revenue share in 2025, while Asia-Pacific is projected to record the fastest CAGR at 39.09% through 2031.

Note: Market size and forecast figures in this report are generated using Mordor Intelligence’s proprietary estimation framework, updated with the latest available data and insights as of January 2026.

Global Disaggregated Memory Architecture For AI Data Centers Market Trends and Insights

Drivers Impact Analysis*

AI Workload Proliferation and Memory Wall Pressure

Large language models and agentic AI systems have pushed memory capacity into the foreground because the limiting factor in many production environments is no longer raw compute alone. The disaggregated memory architecture for the AI data centers market benefits from this shift, since CXL-based pooling extends usable memory beyond DIMM slot limits while preserving standard load-store behavior for servers that need fast access paths. Vendors have also framed memory pressure as a system-level issue, with newer switch and controller designs positioned specifically to break the AI memory wall through shared and expandable memory pools. Meta’s Vistara deployment made the operating case more concrete by showing a 25% reduction in ML inference server counts and a 29% reduction in distributed cache latency when recycled DDR4 was attached over a CXL fabric at hyperscale.[1] That result matters because it shows that the disaggregated memory architecture for the AI data center market is being driven by real production bottlenecks, not by a speculative lab-only use case. As more AI fleets move from pilot clusters to broad deployment, memory efficiency becomes a direct infrastructure issue, which strengthens demand for pooled designs across both hyperscale and cloud environments.

Hyperscale Data Center Transition to Composable Infrastructure

Hyperscalers are gradually shifting from fixed server configurations toward composable designs, where compute, memory, and storage can be scaled with more independence than in traditional racks. That change supports the disaggregated memory architecture for the AI data center market by allowing operators to avoid retiring working memory assets each time a processor platform is refreshed. CXL Consortium modeling presented in 2025 showed that memory costs can fall by 16% to 27% when lower-cost DIMMs are paired with CXL expansion memory, which gives operators a clear financial reason to separate memory planning from CPU refresh cycles. The architectural shift is also evident in public cloud deployments, where Astera Labs’ Leo CXL Smart Memory Controllers were used on Microsoft Azure M-series virtual machines to enable more than 1.5 times the memory capacity per server controller. Research published in 2026 further noted that the CXL ecosystem already spans more than 190 vendors across devices and IP, which means the supplier base needed for composable deployment is now broad enough to support production programs. Even so, the next wave of adoption will depend less on hardware discovery and more on software layers that can place, rebalance, and monitor pooled memory without adding heavy operating complexity.

Tight Coupling of CXL Ecosystem Support Across CPUs, Memory, and Switches

The disaggregated memory architecture for AI data centers market is advancing because CPUs, memory modules, and switch silicon are maturing together instead of in isolation. SK hynix completed customer validation of its 96GB CMM-DDR5 CXL 2.0 memory module in 2025 and began validation of a 128GB product, signaling that larger CXL memory form factors were moving closer to wider deployment. Marvell added another layer of readiness when it launched the Structera S 30260 in March 2026, a 260-lane CXL 3.0 switch built for rack-level pooling with 4TB/s of aggregate bandwidth. Rambus also reached compliance milestones in early 2026, with its CXL 2.0 Controller IP added to the CXL Consortium Integrators List at 16GT/s, which helps downstream adopters shorten at least part of the standards validation process. The larger effect is that the disaggregated memory architecture for the AI data center market is no longer waiting on a single missing hardware layer, because buyers can now evaluate multi-vendor combinations with more confidence than they could a year earlier. This co-maturation also favors vendors that can support multiple CXL generations simultaneously, since large qualification programs often span several platform cycles before full fleet rollout begins.

Rising Demand for Memory Utilization Optimization and Lower TCO

Economic pressure is becoming one of the clearest supports for the disaggregated memory architecture for the AI data centers market, because operators want measurable savings rather than theoretical performance gains. The CXL Consortium showed in 2025 that memory costs can be reduced by 16% to 27% through CXL expansion, giving data center buyers a direct cost case before broader infrastructure benefits are factored in. Meta’s Vistara deployment then extended that logic by showing that CXL-based memory expansion helped support equivalent AI workloads with 20% to 25% fewer servers, with implications for power, cooling, and rack space, as well as memory procurement. The same deployment also showed that recycled DDR4 can be reused in newer environments via CXL fabrics, improving asset utilization and reducing the waste associated with standard server retirement cycles. That mix of lower hardware waste, fewer servers, and better memory use is why the disaggregated memory architecture for the AI data centers market is gaining traction with operators that must improve return on capital while still scaling AI capacity. It also explains why software telemetry and orchestration are becoming more valuable, because buyers want proof that pooled memory is delivering utilization gains after installation rather than only during pre-sale modeling

Restraints Impact Analysis*

Interoperability and Validation Complexity Across Multi-Vendor CXL Stacks

Interoperability remains a real brake on the disaggregated memory architecture for AI data centers market, because production systems must qualify CPUs, modules, retimers, switches, operating systems, and management layers as one stack. The CXL Consortium’s compliance programs provide a useful baseline, but protocol conformance does not eliminate the longer-term work of system-level tuning, workload validation, and failure handling across mixed-vendor combinations. Research from 2026 clearly made this point by showing that, even as the ecosystem expanded to more than 190 vendors, incremental scaling still required careful deployment discipline and practical lessons from real cloud environments. This is one reason the disaggregated memory architecture for AI data centers market remains more accessible to hyperscalers and large cloud providers than to smaller enterprises or colocation operators with thinner validation teams. The qualification burden also stretches purchasing cycles, because buyers are often forced to test several hardware and software combinations before approving a broader rollout. Until multi-vendor interoperability becomes more routine, adoption will continue to move faster in organizations that can absorb multi-quarter validation programs than in buyers that need short and predictable deployment timelines.

Immature Software Orchestration and Memory Tiering Tooling

Software maturity still trails hardware progress, which limits how quickly the disaggregated memory architecture for the AI data centers market can move from point deployments to fleet-wide use. SK hynix integrated its HMSDK software suite with Linux to optimize performance in CXL-enabled systems, but that approach remains vendor-led and, by itself, does not solve control-plane management across mixed hardware environments. Astera Labs has also built telemetry and reliability tools into its COSMOS suite, which helps with visibility, but the broader challenge remains automated policy control across heterogeneous pools and workload classes. Work published in 2026 on LLM serving showed that compute-memory disaggregation can reduce waste and improve cache handling, but it also showed that practical gains depend on well-designed software frameworks rather than hardware attachment alone. That matters because the disaggregated memory architecture for the AI data centers market will not realize its full value if each module supplier, controller vendor, or system builder exposes a separate management layer that buyers must learn and integrate. As long as orchestration remains fragmented, enterprises will keep treating pooled memory as a specialized deployment rather than a standard infrastructure option.

*Our forecasts treat driver/restraint impacts as directional, not additive. The impact forecasts reflect baseline growth, mix effects, and variable interactions.

Segment Analysis

By Component: Software Platforms Move Up the Value Stack

Memory Modules accounted for 44.13% of component revenue in 2025, indicating that most deployments still begin with direct memory expansion before buyers move into more complex switching and fabric designs. That position was supported by the fact that validated CXL memory modules were already moving into customer programs, with SK hynix completing validation of a 96GB CXL 2.0-based CMM-DDR5 product and progressing work on a 128GB version. In the disaggregated memory architecture for the AI data centers market, this entry point makes sense because module-led expansion is easier to qualify than rack-level pooling and requires fewer changes to the current server design. It also helps explain why the hardware revenue base still skews toward modules, even though switches, controllers, and software are attracting growing attention. Switches and retimers matter because they create the path from simple expansion to shared memory pools, where larger efficiency gains begin to emerge.

Controllers and adapters sit in the middle of that transition because they determine how reliably memory can be expanded, monitored, and mapped across different host environments. Integration and Support Services are also becoming a more visible part of the disaggregated memory architecture for AI data centers market, since qualification, tuning, and workload testing often require engineering support beyond standard hardware fulfillment. Software and Management Platforms is projected to grow at a 39.18% CAGR through 2031, which shows that value is beginning to migrate toward the control layer as basic CXL hardware becomes more widely available. Astera Labs’ COSMOS suite reflects that direction by offering link visibility, fleet-level management, and reliability telemetry around its memory controller portfolio. As the disaggregated memory architecture for AI data centers industry matures, buyers in regulated and large-scale environments are likely to switch hardware components faster than they switch orchestration and diagnostic tools, which makes software the stickier layer of the stack.

By Memory Technology: DRAM Leads While Tiered Memory Gains Ground

DRAM held 61.76% of the memory technology segment in 2025, and that dominance reflects its role as the only broad production-ready option for CXL direct-attached expansion with latency that still fits CPU load-store access. In the disaggregated memory architecture for the AI data centers market, DRAM remains the practical first choice because it can expand capacity without forcing applications to shift immediately toward storage-like access patterns. HBM remains important in the wider AI hardware stack, but its near-GPU placement and high cost per bit make it less suited to shared rack-scale disaggregation than to private accelerator memory. Persistent Memory still has a narrower role, mainly in use cases where byte-addressable durability matters more than DRAM-class speed, such as journaling and checkpoint-heavy workflows. That means the segment structure today still reflects operational readiness more than long-run architectural preference.

Tiered Memory, which combines DRAM and NAND, is projected to grow at a 38.97% CAGR through 2031, as it offers a more affordable path to larger, more effective memory pools. Research published in 2026 showed that CXL-hybrid memory systems can expose SSD-backed capacity as direct-access expansion through a DMA-based approach that masks part of NVMe latency, which supports much larger inference state hosting than all-DRAM designs can economically deliver. That matters for the disaggregated memory architecture for AI data centers market because many context-length-sensitive workloads cannot justify an all-DRAM footprint at production scale. It also means software policy will determine segment growth, since tiered memory only works well when page placement, hot data handling, and fallback behavior are managed with discipline. Over time, the segment is likely to broaden not because DRAM loses relevance, but because operators need more than one economic tier inside the same memory hierarchy. The disaggregated memory architecture for AI data centers market therefore keeps DRAM at the core while gradually opening more room for mixed memory classes that balance latency, capacity, and cost.

By Architecture Type: Direct Attached Wins Early, Fabric Attached Sets Direction

Direct Attached Memory Expansion accounted for 51.36% of the disaggregated memory architecture in the AI data center market in 2025, as it is the easiest architecture for conservative buyers to qualify and deploy. A CXL-capable CPU and a compatible expansion module are often enough to get the first deployment running, which lowers both technical and organizational resistance. That is why the disaggregated memory architecture for the AI data center market still leans toward direct attachment in its early phase, even though operators more often speak about pooling and fabrics in their strategic plans. Switched Memory Pooling and Rack-Scale Memory Disaggregation come next, but both require more complex topologies, more software coordination, and a deeper validation effort across hosts and devices. Research in 2026 showed that meaningful pooling gains begin to appear around clusters of 64 servers, while low-latency communication remains manageable within smaller islands of 16 servers, which is shaping how vendors think about pod design.

Fabric Attached Memory is projected to grow at a 38.91% CAGR through 2031, aligning with the longer-term design goal of a composable AI data center. Marvell’s Structera 30260 was launched for that purpose, with 260 lanes and 4 TB/s of aggregate bandwidth, aimed at dynamic memory allocation across CPUs, GPUs, and XPUs. Panmnesia is pushing the same direction with its PCIe 6.4 and CXL 3.2 Fusion Switch, which the company describes as the first silicon to implement CXL 3.2 with port-based routing.[2] The growing presence of such devices shows that the disaggregated memory architecture for AI data centers market is beginning to build the hardware base required for memory access across a broader fabric rather than a single host boundary. Even so, the transition will remain gradual because direct-attached rollouts are still the most practical path for many buyers that want immediate gains without redesigning rack topology. The disaggregated memory architecture for AI data centers industry is therefore likely to run with several architectures in parallel for years, with direct-attached models generating current revenue while fabric-attached designs define the future roadmap.

By Application: Training Holds the Base While Serving Drives Expansion

AI Training accounted for 39.94% of application revenue in 2025, reflecting the large memory footprint required to support model training at scale. This segment led the disaggregated memory architecture for the AI data center market because training workloads were among the first to consistently push server DRAM limits across large deployments. In-Memory Databases and Analytics, as well as High Performance Computing, continue to support demand, since both use cases already have long histories of paying for memory-heavy infrastructure. Enterprise Virtualization remains the smallest and slowest-moving part of the application mix because its memory demand patterns are more predictable, and conventional DDR5 scaling still meets the needs of many deployments. The application split, therefore, shows that urgency is strongest where memory pressure is irregular, large, and expensive to meet with static provisioning.

Large Language Model Serving is projected to grow at a 39.36% CAGR through 2031, as inference workloads create a two-sided memory problem due to longer contexts and more concurrent requests. Symphony, presented at USENIX NSDI in 2026, showed that compute-memory disaggregation can reduce wasted GPU recomputation and improve KV cache handling under pressure through a priority-based eviction framework. Additional 2026 research on sparse-attention systems showed that CXL-based disaggregated KV cache designs can support fine-grained and low-latency access patterns that reduce memory overhead during inference. These results are important for the disaggregated memory architecture for AI data centers market because inference economics are increasingly tied to how efficiently memory can be allocated at run time rather than only to raw accelerator count. They also suggest that pooled DRAM can host rapidly changing cache states while model weights remain on high-bandwidth GPU memory, which improves overall resource use without forcing a single memory tier to do every job. As deployment volumes rise, serving is likely to become one of the strongest practical demand engines for the disaggregated memory architecture for AI data centers market.

By End User: Hyperscalers Define Adoption, CSPs Extend It

Hyperscalers commanded 55.18% of end-user revenue in 2025, which shows that early adoption still depends heavily on fleet scale and engineering depth. That lead is logical because the disaggregated memory architecture for the AI data centers market rewards buyers who can spread qualification costs over large server populations and run internal tests across several vendors at once. Enterprise Data Centers remained the next largest cohort, especially in use cases where expanding memory is more attractive than replacing a full server platform. Colocation Providers and Research and Supercomputing Institutions are smaller in revenue, but they still matter because they can validate new architectures and expose them to a broader buyer base over time. This end-user pattern confirms that adoption begins where complexity can be managed internally, then diffuses outward as the stack becomes more repeatable.

Cloud Service Providers are projected to grow at a 39.11% CAGR through 2031, because they can monetize higher-memory configurations without matching the full capital intensity of hyperscalers. Astera Labs’ deployment on Microsoft Azure M-series virtual machines, which enabled more than 1.5 times the memory capacity per controller, demonstrated how public cloud operators can turn CXL memory expansion into a sellable service layer rather than a back-end experiment. The disaggregated memory architecture for AI data centers market is therefore gaining relevance for second-tier cloud operators that need to close performance and flexibility gaps without matching hyperscaler spending levels. It also creates demand for more standardized telemetry and orchestration, because cloud providers need pooled memory to work within multi-region governance, service-level commitments, and tenant isolation requirements. As that operating discipline spreads, the disaggregated memory architecture for AI data centers market is likely to move from a hyperscaler-first model to a broader cloud-led expansion phase. That progression will matter because cloud providers often translate complex hardware capabilities into simpler service offerings that wider enterprise customers can adopt without managing the full stack themselves.

Complete Report Scope:

• By Component
  • Memory Modules
  • Switches and Retimers
  • Controllers and Adapters
  • Software and Management Platforms
  • Integration and Support Services
• By Memory Technology
  • DRAM
  • HBM
  • Persistent Memory
  • Tiered Memory (DRAM + NAND)
• By Architecture Type
  • Direct Attached Memory Expansion
  • Switched Memory Pooling
  • Rack-Scale Memory Disaggregation
  • Fabric Attached Memory
• By Application
  • AI Training
  • AI Inference
  • High Performance Computing
  • In-Memory Databases And Analytics
  • Large Language Model Serving
  • Enterprise Virtualization
• By End User
  • Hyperscalers
  • Cloud Service Providers
  • Enterprise Data Centers
  • Colocation Providers
  • Research and Supercomputing Institutions
• By Geography
  • North America
    • United States
    • Canada
    • Mexico
  • Europe
    • Germany
    • United Kingdom
    • France
    • Italy
    • Rest of Europe
  • Asia-Pacific
    • China
    • Japan
    • South Korea
    • Taiwan
    • India
    • Rest of Asia-Pacific
  • South America
  • Middle East and Africa

Geography Analysis

North America accounted for 46.28% of the disaggregated memory architecture market share in 2025, reflecting the region’s concentration of hyperscale campuses, semiconductor design firms, and advanced qualification capacity. The region benefits from close proximity among CPU platform developers, memory controller specialists, switch vendors, and some of the world’s largest AI infrastructure operators, which shortens deployment feedback loops. Astera Labs expanded its ecosystem reach in June 2026 by expanding its Taiwan operations and establishing a cloud-scale interoperability laboratory to strengthen its work with Asian system manufacturers and AI platform providers.[3] For North American operators, the 16% to 27% memory cost savings modeled by the CXL Consortium remain especially relevant because rising power costs and mature data center corridors place greater emphasis on efficiency gains than on simple hardware scale. Canada is also emerging as a secondary node through AI-oriented data center investment, while Mexico remains more closely tied to edge and supporting infrastructure than to full-scale pooled memory deployment.

Europe remains smaller in current revenue, but the region is moving forward on a different logic than North America. Data residency requirements and compliance expectations make software-definable infrastructure more attractive, because buyers want visibility into how resources are assigned and governed. Germany and the United Kingdom are leading adoption through a mix of hyperscale presence and enterprise demand from finance, manufacturing, and simulation-heavy workloads. France and Italy are still earlier in the cycle, but national AI and research infrastructure programs are helping create an initial buyer base for more advanced memory topologies. Across the rest of Europe, renewable power availability and continued hyperscaler expansion into Nordic and Eastern European locations are supporting the conditions needed for later-stage adoption.

Asia-Pacific is projected to expand at a 39.09% CAGR through 2031, making it the fastest-growing regional part of the disaggregated memory architecture for AI data centers market. Taiwan continues to anchor the supply chain as the foundry base for leading CXL controllers and switch silicon, which gives the region production depth as well as demand potential. China is building domestic memory capability that can feed state-linked AI infrastructure, while India is still in an earlier capacity-building phase where hyperscaler and cloud investment lay the groundwork for future adoption. South America and the Middle East and Africa are likely to remain behind the global frontier in the near term because lower hyperscale density and higher integration costs make rack-scale CXL deployments harder to justify early.

Competitive Landscape

The disaggregated memory architecture for the AI data center market is moderately concentrated at the top, because Samsung Electronics, SK hynix, and Micron Technology hold strong positions in CXL-compatible memory supply, while controller, retimer, switch, and software revenue is spread across a broader vendor field. That structure creates a clear hardware core, but it does not yet produce full-stack dominance by any one company across the entire value chain. Marvell strengthened its position in February 2026 by completing the acquisition of XConn Technologies for USD 325 million in cash plus approximately 2.7 million Marvell shares, a move that expanded its CXL portfolio to include switches, controllers, and connectivity assets.[4] Astera Labs pursued a different strategy by combining controller hardware with operational software and then tying that package to a visible cloud deployment on Microsoft Azure M-series virtual machines. Montage Technology added another signal in 2026 when it demonstrated a live multi-host CXL 3.2 Dynamic Capacity Device system using its MXC GEN3 silicon, showing that Chinese suppliers are also moving early in memory pooling architectures.

White space remains visible in unified orchestration software, near-data processing inside memory modules, and ARM-based CXL integration. That is why the disaggregated memory architecture for AI data centers market still offers room for companies that are not the largest module suppliers, especially if they can reduce operational friction rather than only increase bandwidth. Astera Labs has already pointed to ARM-linked opportunities through work on PCIe 6 and CXL-enabled AI inference systems, which suggests that x86’s early advantage may not hold forever as AI server architectures diversify. Panmnesia also stands out as an emerging specialist, because it is developing switch silicon aimed at more advanced CXL 3.2 routing and memory-sharing use cases. The disaggregated memory architecture for AI data centers industry therefore still has room for design-win shifts, especially in layers where software support and topology control matter as much as the base memory device.

Standards progress also keeps the field open enough to prevent early lock-in from becoming absolute. Rambus advanced its position through compliance work and new controller IP, which helps it compete where buyers need a standards-aligned building block rather than a complete memory product. Broadcom used OFC 2026 to showcase PCIe Gen6 switches, retimers, and its Atlas 4 PCIe Gen7 and CXL switch, reinforcing how established connectivity firms are entering the segment from adjacent infrastructure positions. The disaggregated memory architecture for AI data centers market will likely stay moderately concentrated rather than highly consolidated in the near term, because value is still split across modules, controllers, switches, software, and integration services. That balanced structure is likely to persist until buyers begin standardizing on a smaller set of software control layers and fabric topologies across full production fleets.

Recent Industry Developments

• June 2026: Montage Technology demonstrated the first live multi-host CXL 3.2 Dynamic Capacity Device system using its MXC GEN3 silicon at the CXL Consortium, validating memory pooling and sharing across multiple hosts for production-ready deployment.
• June 2026: Astera Labs expanded its Taiwan operations and cloud-scale interoperability laboratory to strengthen AI system integration with leading AI platform providers and Taiwanese system manufacturers.
• March 2026: Marvell Technology launched the Structera S 30260, a 260-lane CXL 3.0 switch with 4TB/s aggregate bandwidth, at OFC 2026 in Los Angeles. The device enables rack-level memory pooling and dynamic memory allocation across CPUs, GPUs, and XPUs. Customer sampling is expected to begin in Q3 2026.
• March 2026: Rambus announced the industry’s leading HBM4E Memory Controller IP, extending its portfolio to address next-generation AI accelerator and GPU memory bandwidth requirements with advanced reliability features.

List of Companies Covered in this Report:

• Samsung Electronics Co., Ltd.
• SK hynix Inc.
• Micron Technology, Inc.
• Intel Corporation
• Advanced Micro Devices, Inc.
• Broadcom Inc.
• Marvell Technology, Inc.
• Astera Labs, Inc.
• Rambus Inc.
• Montage Technology Co., Ltd.
• Super Micro Computer, Inc.
• Dell Technologies Inc.
• Hewlett Packard Enterprise Company
• Lenovo Group Limited
• GigaIO, Inc.
• MemVerge, Inc.
• Liqid, Inc.
• Quanta Computer Inc.

Additional Benefits:

• The market estimate (ME) sheet in Excel format
• 3 months of analyst support

Table of Contents

1 INTRODUCTION
1.1 Study Assumptions and Market Definition
1.2 Scope of the Study

2 RESEARCH METHODOLOGY

3 EXECUTIVE SUMMARY

4 MARKET LANDSCAPE
4.1 Market Overview
4.2 Market Drivers
4.2.1 AI Workload Proliferation and Memory Wall Pressure
4.2.2 Hyperscale Data Center Transition to Composable Infrastructure
4.2.3 Tight Coupling of CXL Ecosystem Support Across CPUs, Memory, and Switches
4.2.4 Rising Demand for Memory Utilization Optimization and Lower TCO
4.2.5 Emerging Need for Rack-Scale Resource Pooling In Multi-Tenant AI Clusters
4.2.6 Faster Qualification of CXL 3.x Platforms for Production Deployment
4.3 Market Restraints
4.3.1 Interoperability and Validation Complexity Across Multi-Vendor CXL Stacks
4.3.2 Immature Software Orchestration and Memory Tiering Tooling
4.3.3 High Integration Cost for Rack-Scale Fabric, Switch, and Memory Pooling Hardware
4.3.4 Risk of Delayed Adoption Where HBM and DDR Roadmaps Still Meet Near-Term Needs
4.4 Industry Value Chain Analysis
4.5 Regulatory Landscape
4.6 Technological Outlook
4.7 Porter’s Five Forces Analysis
4.7.1 Bargaining Power of Buyers
4.7.2 Bargaining Power of Suppliers
4.7.3 Threat of New Entrants
4.7.4 Threat of Substitutes
4.7.5 Intensity of Competitive Rivalry
4.8 Impact of Macroeconomic Factors on the Market

5 MARKET SIZE AND GROWTH FORECASTS (VALUE)
5.1 By Component
5.1.1 Memory Modules
5.1.2 Switches and Retimers
5.1.3 Controllers and Adapters
5.1.4 Software and Management Platforms
5.1.5 Integration and Support Services
5.2 By Memory Technology
5.2.1 DRAM
5.2.2 HBM
5.2.3 Persistent Memory
5.2.4 Tiered Memory (DRAM + NAND)
5.3 By Architecture Type
5.3.1 Direct Attached Memory Expansion
5.3.2 Switched Memory Pooling
5.3.3 Rack-Scale Memory Disaggregation
5.3.4 Fabric Attached Memory
5.4 By Application
5.4.1 AI Training
5.4.2 AI Inference
5.4.3 High Performance Computing
5.4.4 In-Memory Databases And Analytics
5.4.5 Large Language Model Serving
5.4.6 Enterprise Virtualization
5.5 By End User
5.5.1 Hyperscalers
5.5.2 Cloud Service Providers
5.5.3 Enterprise Data Centers
5.5.4 Colocation Providers
5.5.5 Research and Supercomputing Institutions
5.6 By Geography
5.6.1 North America
5.6.1.1 United States
5.6.1.2 Canada
5.6.1.3 Mexico
5.6.2 Europe
5.6.2.1 Germany
5.6.2.2 United Kingdom
5.6.2.3 France
5.6.2.4 Italy
5.6.2.5 Rest of Europe
5.6.3 Asia-Pacific
5.6.3.1 China
5.6.3.2 Japan
5.6.3.3 South Korea
5.6.3.4 Taiwan
5.6.3.5 India
5.6.3.6 Rest of Asia-Pacific
5.6.4 South America
5.6.5 Middle East and Africa

6 COMPETITIVE LANDSCAPE
6.1 Market Concentration
6.2 Strategic Moves
6.3 Market Share Analysis
6.4 Company Profiles (includes Global Level Overview, Market Level Overview, Core Segments, Financials as available, Strategic Information, Market Rank/Share, Products and Services, Recent Developments)
6.4.1 Samsung Electronics Co., Ltd.
6.4.2 SK hynix Inc.
6.4.3 Micron Technology, Inc.
6.4.4 Intel Corporation
6.4.5 Advanced Micro Devices, Inc.
6.4.6 Broadcom Inc.
6.4.7 Marvell Technology, Inc.
6.4.8 Astera Labs, Inc.
6.4.9 Rambus Inc.
6.4.10 Montage Technology Co., Ltd.
6.4.11 Super Micro Computer, Inc.
6.4.12 Dell Technologies Inc.
6.4.13 Hewlett Packard Enterprise Company
6.4.14 Lenovo Group Limited
6.4.15 GigaIO, Inc.
6.4.16 MemVerge, Inc.
6.4.17 Liqid, Inc.
6.4.18 Quanta Computer Inc.

7 MARKET OPPORTUNITIES AND FUTURE OUTLOOK
7.1 White Space and Unmet Need Assessment

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